Verification Engineer Salary at Rivos Inc BETA

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools. Job Description/Responsibilities The successful candidate will contribute to the verification and validation of FPGA cores and related ASIC subsystems implemented in modern FPGA technology nodes (7nm and below). Responsibilities include the following: Verify ASIC logic subsystems developed for high-speed networking and data center applications for inclusion in modern FPGAs Define, draft and review verification documents and testplans in collaboration wi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi

Job Title: Verification Engineer Location: Santa Clara, CA (3 days onsite) Duration: 12+ months JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team , working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the UVM testbench development, test plan & verification of a Complex SOC Responsibilities: Create and implement a verification plan. Develop and execute test cases to ensure the functionality, performance, and reliability of the chip design. Collaborate with the hardware design team to identify and resolve issues. Work in a UVM environment. Use of Assertions, and randomized and direct tests. Code coverage and debugging. Analyze and report on verification results. Qualifications: 10-15 years of solid experience in UVM design verifi