Digital Designer Salary at Omneky Inc BETA

Job Title: Emulation Design Engineer Location: San Jose, CA (5 days onsite) Duration: 12+ months Experience: 8+ years (Relevant) Note: For HAPS or EMULATION – Should have Model build and DESIGN along with integration and development. Able to Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. What we are looking for: A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs acr

Job Title: Emulation Design Engineer Location: San Jose, CA (5 days onsite) Duration: 12+ months Experience: 8+ years (Relevant) Note: For HAPS or EMULATION – Should have Model build and DESIGN along with integration and development. Able to Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. What we are looking for: A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs acr

At Serve Robotics, we're reimagining how things move in cities. Our personable sidewalk robot is our vision for the future. It's designed to take deliveries away from congested streets, make deliveries available to more people, and benefit local businesses. The Serve fleet has been delighting merchants, customers, and pedestrians along the way in Los Angeles while doing commercial deliveries. We're looking for talented individuals who will grow robotic deliveries from surprising novelty to efficient ubiquity. Who We Are We are tech industry veterans in software, hardware, and design who are pooling our skills to build the future we want to live in. We are solving real-world problems leveraging robotics, machine learning and computer vision, among other disciplines, with a mindful eye towards the end-to-end user experience. Our team is agile, diverse, and driven. We believe that the best way to solve complicated dynamic problems is collaboratively and respectfully. About The Team The dy

Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or a related field. Experience: Proven experience in RTL design and integration (using Verilog, VHDL, or SystemVerilog). Hands-on experience with digital design verification and subsystem integration. Experience with quality assurance tools and processes for RTL code. Knowledge of front-end design flow including synthesis, linting, and static analysis. Technical Skills: Strong proficiency in RTL coding languages: Verilog, VHDL, or SystemVerilog. Experience with EDA tools (e.g., Cadence, Synopsys, Mentor Graphics). Familiarity with simulation tools (e.g., ModelSim, VCS, Xcelium). Experience with debugging and troubleshooting integration issues in RTL designs. Strong understanding of timing analysis and timing closure.

Job Title: Emulation Design Engineer Location: San Jose, CA (5 days onsite) Duration: 12+ months Experience: 8+ years (Relevant) Note: For HAPS or EMULATION – Should have Model build and DESIGN along with integration and development. Able to Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. What we are looking for: A Bachelor's Degree in Electrical or Computer Engineering, accompanied by a minimum of 10 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. A comprehensive understanding of FPGA design, with proven expertise in partitioning multi-million gate designs acr

Job Title: Analog/Mixed-Signal IC Design Engineer Location: Fremont, California, United States Duration: Full Time Role ROLES & RESPONSIBILITIES: Design and development of high-performance analog integrated circuits, including amplifiers, data converters, voltage regulators, and other analog signal processing circuits. Conduct detailed design simulations, verification, and validation to ensure circuit performance meets specifications and quality standards. Collaborate with cross-functional teams, including digital designers, layout engineers, and system architects, to ensure seamless integration of analog and digital components. Drive innovation by researching and implementing advanced design techniques, methodologies, and emerging technologies. Mentor and provide technical guidance to junior engineers, fostering a culture of continuous learning and professional development. Participate in design reviews, provide constructive feedback, and contribute to the improvement of design proces

High-speed Analog/Mixed-Signal IC Design Engineer – Bay Area An exciting opportunity has emerged for an experienced Analog/Mixed-Signal IC Design Engineer to join a cutting-edge technology company at the forefront of innovation in semiconductor design. This firm, based in the Bay Area, is driving advancements in high-speed, high-performance analog and mixed-signal integrated circuits, with applications spanning multiple high-growth industries. Key Responsibilities: Lead the design and development of high-performance analog integrated circuits, including amplifiers, data converters, voltage regulators, and other critical signal processing components. Conduct detailed circuit design simulations, verification, and validation to ensure superior performance and reliability. Collaborate cross-functionally with digital design, layout, and system architecture teams to ensure seamless integration of analog and digital components. Innovate by researching and implementing advanced design methodol

**Location:** Must reside in San Jose CA (Bay Area) **Responsibilities:** You will be the primary point of contact with customers from a technical perspective. Responsible for SoC Architecture but you will not be involved with the day-to-day details of the design. Develop architecture and micro-architecture from specs (Full chip design for multimillion gates SoC) Manage IP dependencies, planning and tracking of all front-end design related tasks. Drive project milestones across the design, verification, and physical implementations. Manage interface with Value Chain Aggregator partners for manufacturing and testing. Manage design from architecture to tape-out, foundry and outside semiconductor assembly & test (OSAT). Responsible for determining the types of internal resources required for projects. **Required Qualifications:** Strong understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure, top level test plans, and verificat